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features ? 262,144 bytes by 8-bit organization ? fast access time: 90/120 ns ? low power consumption C 50ma maximum active current C 100ua maximum standby current ? programming and erasing voltage 12v 5% ? command register architecture C byte programming (15us typical) C auto chip erase 5 seconds typical (including preprogramming time) C block erase ? optimized high density blocked architecture C eight 4-kb blocks C fourteen 16-kb blocks 1 p/n: pm0472 ? auto erase (chip & block) and auto program C data polling C toggle bit ? 10,000 minimum erase/program cycles ? latch-up protected to 100ma from -1 to vcc+1v ? advanced cmos flash memory technology ? compatible with jedec-standard byte-wide 32-pin eprom pinouts ? package type: C 32-pin plastic dip C 32-pin plcc rev. 1.0, jun 13, 1997 general description the mx28f2000t is a 2-mega bit flash memory or- ganized as 256k bytes of 8 bits each. mxic's flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. the mx28f2000t is packaged in 32-pin pdip and plcc . it is designed to be reprogrammed and erased in- system or in-standard eprom programmers. the standard mx28f2000t offers access times as fast as 90 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention, the mx28f2000t has separate chip enable (ce) and output enable (oe) controls. mxic's flash memories augment eprom function- ality with in-circuit electrical erasure and programming. the mx28f2000t uses a command register to manage this functionality, while maintaining a standard 32-pin pinout. the command register allows for 100% ttl level control inputs and fixed power supply levels during erase and programming, while maintaining maximum eprom compatibility. mxic flash technology reliably stores memory con- tents even after 10,000 erase and program cycles. the mxic cell is designed to optimize the erase and programming mechanisms. in addition, the combi- nation of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the mx28f2000t uses a 12.0v 5% vpp supply to perform the auto program/erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v. mx28f2000t 2m-bit [256k x 8] cmos flash memory
2 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 mx28f2000p block address and block structure 3ffffh a17~a0 3d000h 3f000h 3e000h 3c000h 3b000h 39000h 4-k byte 4-k byte 4-k byte 4-k byte 16-k byte 16-k byte 16-k byte 16-k byte 16-k byte 16-k byte 16-k byte 16-k byte 16-k byte 00000h 16-k byte 3a000h 38000h 3efffh 3dfffh 3cfffh 3bfffh 3afffh 39fffh 38fffh 37fffh 34000h 33fffh 30000h 2ffffh 2c000h 2bfffh 28000h 27fffh 24000h 23fffh 20000h 1ffffh 1c000h 1bfffh 18000h 17fffh 14000h 13fffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 04000h 03fffh 4-k byte 4-k byte 4-k byte 4-k byte 16-k byte 16-k byte 16-k byte 16-k byte
3 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 pin configurations 32 pdip 32 plcc symbol pin name a0~a17 address input q0~q7 data input/output ce chip enable input oe output enable input we write enable pin vpp program supply voltage vcc power supply pin (+5v) gnd ground pin pin description: mx28f2000t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vpp a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc we a17 a14 a13 a8 a9 a11 oe a10 ce q7 q6 q5 q4 q3 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe a10 ce q7 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 vss q3 q4 q5 q6 a12 a15 a16 vpp vcc we a17 mx28f2000t
4 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 block diagram control input logic program/erase high voltage mode logic s tat e register mx28f2000t flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q7 a0-a17 ce oe we
5 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 automatic programming the mx28f2000t is byte programmable using the automatic programming algorithm. the automatic programming algorithm does not require the system to time out or verify the data programmed. the typical room temperature chip programming time of the mx28f2000t is less than 5 seconds. automatic chip erase the device may be erased using the automatic erase algorithm. the automatic erase algorithm automati- cally programs the entire array prior to electrical erase. the timing and verification of electrical erase are controlled internal to the device. automatic block erase the mx28f2000t is block(s) erasable using mxic's auto block erase algorithm. block erase modes allow blocks of the array to be erased in one erase cycle. the automatic block erase algorithm automatically programs the specified block(s) prior to electrical erase. the timing and verification of electrical erase are controlled internal to the device. automatic programming algorithm mxic's automatic programming algorithm requires the user to only write a program set-up command and a program command (program data and address). the device automatically times the programming pulse width, provides the program verify, and counts the number of sequences. a status bit similar to data polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. mxic's automatic erase algorithm requires the user to only write an erase set-up command and erase com- mand. the device will automatically pre-program and verify the entire array. then the device automatically times the erase pulse width, provides the erase verify, and counts the number of sequences. a status bit similar to data polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the erase operation. commands are written to the command register using standard microprocessor write timings. register con- tents serve as inputs to an internal state-machine which controls the erase and programming circuitry. during write cycles, the command register internally latches address and data needed for the programming and erase operations. for system design simplifica- tion, the mx28f2000t is designed to support either we or ce controlled writes. during a system write cycle, addresses are latched on the falling edge of we or ce whichever occurs last. data is latched on the rising edge of we or ce whichever occur first. to simplify the following discussion, the we pin is used as the write cycle control pin throughout the rest of this text. all setup and hold times are with respect to the we signal. mxic's flash technology combines years of eprom experience to produce the highest levels of quality, relia- bility, and cost effectiveness. the mx28f2000p electri- cally erases all bits simultaneously using fowler-nord- heim tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection. automatic erase algorithm
6 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 table 1. command definitions command bus first bus cycle second bus cycle cycles operation address data operation address data read memory 1 write x 00h read identified codes 2 write x 90h read ia id setup auto erase/ 2 write x 30h write x 30h auto erase (chip) setup auto erase/ 2 write x 20h write ea d0h auto erase (block) setup auto program/ 2 write x 40h write pa pd program setup erase/ 2 write x 20h write x 20h erase (chip) setup erase/ 2 write x 60h write ea 60h erase (block) erase verify 2 write eva a0h read x evd reset 2 write x ffh write x ffh note: ia = identifier address ea = block of memory location to be erased pa = address of memory location to be pro- grammed id = data read from location ia during device iden- tification pd = data to be programmed at location pa eva = address of memory location to be read during erase verify. evd = data read from location eva during erase verify. auto modes have the build-in enchanced features. please use the auto erase mode whenever it is.
7 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 command definitions when low voltage is applied to the vpp pin, the con- tents of the command register default to 00h, enabling read-only operation. placing high voltage on the vpp pin enables read/write operations. device operations are selected by writing specific data patterns into the command register. ta- ble 1 defines these mx28f2000t register commands. table 2 defines the bus operations of mx28f2000t. table 2. mx28f2000t bus operations operation vpp(1) a0 a9 ce oe we dq0-dq7 read-only read vppl a0 a9 vil vil vih data out output disable vppl x x vil vih vih tri-state standby vppl x x vih x x tri-state read silicon id (mfr)(2) vppl vil vid(3) vil vil vih data = c2h read silicon id (device)(2) vppl vih vid(3) vil vil vih data = 3ch read/write read vpph a0 a9 vil vil vih data out(4) standby(5) vpph x x vih x x tri-state write vpph a0 a9 vil vih vil data in(6) notes: 1. vppl may be grounded, a no-connect with a resistor tied to ground, or < vcc + 2.0v. vpph is the programming voltage specified for the device. when vpp = vppl, memory contents can be read but not written or erased. 2. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 1. all other addresses don't care. 3. vid is the silicon-id-read high voltage.(11.5v to 13v) 4. read operations with vpp = vpph may access array data or silicon id codes. 5. with vpp at high voltage, the standby current equals icc + ipp (standby). 6. refer to table 1 for valid data-in during a write operation. 7. x can be vil or vih.
8 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 pattern. when the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. the erase and verify operations are complete when the data on dq7 is "1" at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic chip erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verify command is required). the margin voltages are internally generated in the same manner as when the standard erase verify command is used. the automatic set-up erase command is a command- only operation that stages the device for automatic electrical erasure of all bytes in the array. automatic set-up erase is performed by writing 30h to the command register. to command automatic chip erase, the command 30h must be written again to the command register. the automatic chip erase begins on the rising edge of the we and terminates when the data on dq7 is "1" and the data on dq6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode. the automatic block erase does not require the device to be entirely pre-programmed prior to executing the automatic set-up block erase command and automatic block erase command. upon executing the automatic block erase command, the device automati- cally will program and verify the block(s) memory for an all-zero data pattern. the system is not required to provide any controls or timing during these operations. when the block(s) is automatically verified to contain an all-zero pattern, a self-timed block erase and verify begin. the erase and verify operations are complete when the data on dq7 is "1" and the data on dq6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. read command while vpp is high, for erasure and programming, memory contents can also be accessed via the read command. the read operation is initiated by writing 00h into the command register. microprocessor read cycles retrieve array data. the device remains en- abled for reads until the command register contents are altered. the default contents of the register upon vpp power- up is 00h. this default value ensures that no spurious alteration of memory contents occurs during the vpp power transition. where the vpp supply is hard-wired to the mx28f2000t, the device powers up and remains enabled for reads until the command register contents are changed. silicon-id-read command flash-memories are intended for use in applications where the local cpu alters memory contents. as such, manufacturer- and device-codes must be accessible while the device resides in the target system. prom programmers typically access signature codes by rais- ing a9 to a high voltage. however, multiplexing high voltage onto address lines is not a desired system- design practice. the mx28f2000t contains a silicon-id-read opera- tion to supplement traditional prom-programming methodology. the operation is initiated by writing 90h into the command register. following the command write, a read cycle from address 0000h retrieves the manufacturer code of c2h. a read cycle from address 0001h returns the device code of 3ch. set-up automatic chip erase/erase commands the automatic chip erase does not require the device to be entirely pre-programmed prior to excuting the automatic set-up erase command and automatic chip erase command. upon executing the automatic chip erase command, the device automatically will program and verify the entire memory for an all-zero data set-up automatic block erase/erase commands
9 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 when using the automatic block erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). the margin voltages are internally generated in the same manner as when the standard erase verify command is used. the automatic set-up block erase command is a com- mand only operation that stages the device for auto- matic electrical erasure of selected blocks in the array. automatic set-up block erase is performed by writing 20h to the command register. to enter automatic block erase, the user must write the command d0h to the command register. block addresses are loaded into internal register on the 2nd falling edge of we. each successive block load cycles, started by the falling edge of we, must begin within 30us from the rising edge of the preceding we. otherwise, the loading period ends and internal auto block erase cycle starts. when the data on dq7 is "1" and the data on dq6 stops toggling for two consecutive read cycles, at which time auto erase ends and the device returns to the read mode. refer to page 2 for detailed block address. set-up automatic program/program commands the automatic set-up program is a command-only operation that stages the device for automatic pro- gramming. automatic set-up program is performed by writing 40h to the command register. once the automatic set-up program operation is per- formed, the next we pulse causes a transition to an active programming operation. addresses are internally latched on the falling edge of the we pulse. data is internally latched on the rising edge of the we pulse. the rising edge of we also begins the programming operation. the system is not required to provide further controls or timings. the device will automatically provide an adequate internally generated program pulse and verify margin. the automatic programming operation is completed when the data read on dq6 stops toggling for two consecutive read cycles and the data on dq7 and dq6 are equivalent to data written to these two bits, at which time the device returns to the read mode (no program verify command is required). reset command a reset command is provided as a means to safely abort the erase- or program-command sequences. following either set-up command (erase or program) with two consecutive writes of ffh will safely abort the operation. memory contents will not be altered. should program-fail or erase-fail happen, two consecutive writes of ffh will reset the device to abort the operation. a valid command must then be written to place the device in the desired state. write operaton status toggle bit-dq6 the mx28f2000t features a "toggle bit" as a method to indicate to the host sytem that the auto program/ erase algorithms are either in progress or completed. while the automatic program or erase algorithm is in progress, successive attempts to read data from the device will result in dq6 toggling between one and zero. once the automatic program or erase algorithm is completed, dq6 will stop toggling and valid data will be read. the toggle bit is valid after the rising edge of the second we pulse of the two write pulse sequences. data polling-dq7 the mx28f2000t also features data polling as a method to indicate to the host system that the automatic program or erase algorithms are either in progress or completed. while the automatic programming algorithm is in op- eration, an attempt to read the device will produce the complement data of the data last written to dq7. upon completion of the automatic program algorithm an attempt to read the device will produce the true data last written to dq7. the data polling feature is valid after the rising edge of the second we pulse of the two write pulse sequences.
10 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 while the automatic erase algorithm is in operation, dq7 will read "0" until the erase operation is com- pleted. upon completion of the erase operation, the data on dq7 will read "1". the data polling feature is valid after the rising edge of the second we pulse of two write pulse sequences. the data polling feature is active during automatic program/erase algorithms. power-up sequence the mx28f2000t powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of a two-step command sequence. power up sequence is not required. system considerations during the switch between active and standby condi- tions, transient current peaks are produced on the rising and falling edges of chip enable. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. at a minimum, a 0.1uf ceramic capacitor (high frequency, low inherent inductance) should be used on each device between vcc and gnd, and between vpp and gnd to minimize transient effects. in addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on flash memory arrays, a 4.7uf bulk electrolytic capacitor should be used between vcc and gnd for each eight devices. the location of the capacitor should be close to where the power supply is con- nected to the array.
11 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 absolute maximum ratings rating value ambient operating temperature 0 o c to 70 o c storage temperature -65 o c to 125 o c applied input voltage -0.5v to 7.0v applied output voltage -0.5v to 7.0v vcc to ground potential -0.5v to 7.0v a9 & vpp -0.5v to 13.5v notice: stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is stress rating only and functional operational sections of this specification is not implied. exposure to ab- solute maximum rating conditions for extended period may affect reliability. notice: specifications contained within the following tables are sub- ject to change. capacitance ta = 25 o c, f = 1.0 mhz symbol parameter min. typ max. unit conditions cin input capacitance 14 pf vin = 0v cout output capacitance 16 pf vout = 0v read operation dc characteristics ta = 0 o c to 70 o c, vcc = 5v 10%, vpp = gnd to vcc symbol parameter min. typ max. unit conditions ili input leakage current 10 ua vin = gnd to vcc ilo output leakage current 10 ua vout = gnd to vcc ipp1 vpp current 1 100 ua vpp = 5.5v isb1 standby vcc current 1 ma ce = vih isb2 1 100 ua ce = vcc + 0.3v icc1 operating vcc current 30 ma iout = 0ma, f=1mhz icc2 50 ma iout = 0ma, f=11mhz vil input low voltage -0.3 (note 1) 0.8 v vih input high voltage 2.4 vcc + 0.3 v vol output low voltage 0.45 v iol = 2.1ma voh output high voltage 2.4 v ioh = -400ua notes: 1. vil min. = -1.0v for pulse width < 50 ns. vil min. = -2.0v for pulse width < 20 ns. 2. vih max. = vcc + 1.5v for pulse width < 20 ns if vih is over the specified maximum value, read operation cannot be guaranteed.
12 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 ac characteristics ta = 0 o c to 70 o c, vcc = 5v 10%, vpp = gnd to vcc 28f2000t-90 28f2000t-12 symbol parameter min. max. min. max. unit conditions tacc address to output delay 90 120 ns ce=oe=vil tce ce to output delay 90 120 ns oe=vil toe oe to output delay 40 50 ns ce=vil tdf oe high to output float ( note1) 0 20 0 30 ns ce=vil toh address to output hold 0 0 ns ce=oe=vil note: 1. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven. test conditions: ? input pulse levels: 0.45v/2.4v ? input rise and fall times: < 10ns ? output load: 1 ttl gate + 100pf (including scope and jig) ? reference levels for measuring timing: 0.8v, 2.0v read timing waveforms address we oe ce toh tdf tacc toe tce active mode standby mode standby mode data out data out valid
13 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 command programming/data programming/erase operation dc characteristics ta = 0 o c to 70 o c, vcc = 5v 10%, vpp = 12.0v 5% symbol parameter min. typ max. unit conditions ili input leakage current 10 ua vin=gnd to vcc ilo output leakage current 10 ua vout=gnd to vcc isb1 standby vcc current 1 ma ce=vih isb2 1 100 ua ce=vcc 0.3v icc1 (read) operating vcc current 30 ma iout=0ma, f=1mhz icc2 50 ma iout=0ma, f=11mhz icc3 (program) 50 ma in programming icc4 (erase) 50 ma in erase icc5 (program verify) 50 ma in program verify icc6 (erase verify) 50 ma in erase verify ipp1 (read) vpp current 100 ua vpp=12.6v ipp2 (program) 50 ma in programming ipp3 (erase) 50 ma in erase ipp4 (program verify) 50 ma in program verify ipp5 (erase verify) 50 ma in erase verify vil input voltage -0.3 (note 5) 0.8 v vih 2.4 vcc+0.3v v (note 6) vol output voltage 0.45 v iol=2.1ma voh 2.4 v ioh=-400ua notes: 1. vcc must be applied before vpp and removed after vpp. 2. vpp must not exceed 14v including overshoot. 3. an influence may be had upon device reliability if the device is installed or removed while vpp=12v. 4. do not alter vpp either vil to 12v or 12v to vil when ce=vil. 5. vil min. = -0.6v for pulse width < 20ns. 6. if vih is over the specified maximum value, programming operation cannot be guranteed. 7. all currents are in rms unless otherwise noted.(sampled, not 100% tested.)
14 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 ac characteristics ta = 0 o c to 70 o c, vcc = 5v 10%, vpp =12v 5% 28f2000t-90 28f2000t-12 symbol parameter min. max. min. max. unit contions tvps vpp setup time 100 100 ns toes oe setup time 100 100 ns tcwc command programming cycle 90 120 ns tcep we programming pulse width 45 50 ns tceph1 we programming pluse width high 20 20 ns tceph2 we programming pluse width high 100 100 ns tas address setup time 0 0 ns tah address hold time 45 50 ns tah1 address hold time for data polling 0 0 ns tds data setup time 45 50 ns tdh data hold time 10 10 ns tcesp ce setup time before data polling/toggle bit 100 100 ns tces ce setup time 0 0 ns tcesc ce setup time before command write 100 100 ns tcesv ce setup time before verify 6 6 us tvph vpp hold time 100 100 ns tdf output disable time (note 3) 20 30 ns tdpa data polling/toggle bit access time 90 120 ns taetc total erase time in auto chip erase 5(typ.) 5(typ. ) s taetb total erase time in auto block erase 5(typ.) 5(typ.) s tavt total programming time in auto verify 15 300 15 300 us tbalc block address load cycle 0.3 30 0.3 30 us tbal block address load time 100 100 us tch ce hold time 0 0 ns tcs ce setup to we going low 0 0 ns notes: 1. ce and oe must be fixed high during vpp transition from 5v to 12v or from 12v to 5v. 2. refer to read operation when vpp=vcc about read opera- tion while vpp 12v. 3. tdf defined as the time at which the output achieves the open circuit condition and data is no longer driven.
15 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 switching test circuits switching test waveforms device under test diodes=in3064 or equivalent cl 6.2k ohm 1.8k ohm +5v cl=35pf including jig capacitance 2.0v 2.4 v 0.45 v 0.8v test points input 2.0v 0.8v output ac testing: inputs are driven at 2.4v for a logic "1" and 0.45v for a logic "0". input pulse rise and fall times are <20ns.
16 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 automatic programming timing waveform one byte data is programmed. verify in fast algorithm and additional programming by external control are not required because these operations are excuted auto- matically by internal control circuit. programming completion can be verified by data polling and toggle bit checking after automatic verify starts. device outputs data during programming and data after programming on q7. q0 to q5 (q6 is for toggle bit; see toggle bit, data polling, timing waveform) are in high impedance. tcwc address valid tas tcep toes tcep tcesp tces tcesc tds tdh tdh tds tdf data in command in data in command in vcc 5v ce oe tavt 12v vpp 0v command #40h tvph tvps q7 q0~q5 data polling auto program & data polling setup auto program/ program command data data we a0 ~ a17 tceph1 tah1 data tdpa
17 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 automatic programming algorithm flowchart start apply vpph write set up auto program command (40h) no toggle bit checking dq6 not toggled write auto program command(a/d) last byte auto program completed yes yes no verify byte ok auto program failed no yes reset
18 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 erase starts. device outputs 0 during erasure and 1 after erasure on q7. q0 to q5 (q6 is for toggle bit; see toggle bit, data polling, timing waveform) are in high imped- ance. automatic chip erase timing waveform all data in chip are erased. external erase verify is not required because data is erased automatically by internal control circuit. erasure completion can be verified by data polling and toggle bit checking after automatic tcwc tcep toes tcep tcesp tces tcesc tds tdh tdh tds tdf command in command in vcc 5v ce oe taetc command in command in 12v vpp 0v command #30h command #30h tvph tvps q7 q0~q5 auto chip erase & data polling data polling a0 ~ a17 we tceph1 setup auto chip erase/ erase command tdpa
19 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 automatic chip erase algorithm flowchart start apply vpph write set up auto chip erase command (30h) toggle bit checking dq6 not toggled write auto chip erase command(30h) data polling dq7 = 1 auto chip erase completed yes yes auto chip erase failed reset no no
20 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 checking after automatic erase starts. device outputs 0 during erasure and 1 after erasure on q7. q0 to q5 (q6 is for toggle bit; see toggle bit, data polling, timing waveform) are in high impedance. automatic block erase timing waveform block data indicated by a12 to a17 are erased. external erase verify is not required because data are erased automatically by internal control circuit. erasure comple- tion can be verified by data polling and toggle bit *refer to page 2 for detailed block address. vcc 5v tcep toes tdf command in oe command in command in command in tcesc tds tdh tds tdh block address 0 block address 1 tcwc tas tah tbalc tcep 12v vpp 0v block address # command #20h command #d0h tvph tvps tbal taetb q7 q0~q5 auto block erase & data polling data polling a12 ~ a17 ce we tceph2 tceph1 tch tcs tah1 setup auto block erase/erase command tdpa a0 ~ a11
21 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 automatic block erase algorithm flowchart start apply vpph write set up auto block erase command (20h) no write auto block erase command(d0h) to load block address toggle bit checking dq6 not toggled auto block erase completed yes last block to erase wait 200 us yes data polling dq7 = 1 reset auto block erase failed no no yes load block address
22 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 compatible chip erase timing waveform all data in chip are erased. control verification and additional erasure externally according tocompatible chip erase flowchart. vcc 5v tcep toes tdf command in ce oe command in tcesc tcep tds tdh tds tdh tcwc tet tcep tces tva command in command in tds 12v vpp 0v command #20h command #20h command #a0h tvph tvps q7 q0~q6 erase verify chip erase tas tah verify address tcesv command in command in tdh data valid data valid a0 ~ a17 we tceph1 setup chip erase/ erase command
23 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 compatible block erase this device can be applied to the compatible block erase algorithm shown in the following flowchart. this algorithm allows to obtain faster erase time by the block (refer to page2) without any voltage stress to the device nor deterioration in reliability of data. block erase flow compatible block erase flowchart start end no yes fail all bits verified n = 0 block erase flow ersvfy flow n = 1024? block erase fail apply vpp = vcc block erase complete n = n+1 for selected block(s), all bits pgm"0" start apply write setup block erase command end vpp = vpph write block erase command ( 60h ) wait 10 ms ( load first sector address , 60h ) load other sectors' address if necessary ( load other sector address )
24 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 erase verify flow start write erase verify command wait 6 us last address ? increment address no yes no yes apply vpp = vpph address = first address of erased blocks or last verify failed address ( a0h ) ersvfy ffh ? erase verify complete go to erase flow again or abort
25 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 compatible block erase timing waveform indicated block data are erased. control verification and additional erasure externally according to compatible block erase flowchart. vcc 5v tds tdf command in command in tds tdh tds tdh tva command in command in command in command in tdh tbal tet tcep tas tah tcesc toes tcep tcep tcwc tbalc block address 0 block address 1 tas tah a0 ~ a13 ce oe 12v vpp 0v command #60h command #60h command #a0h tvph tvps q7 q0~q6 erase verify block erase tcesv tces data valid data valid verify address verify address a14 ~ a17 we block address # tceph1 tceph2 setup block erase/erase command
26 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 vpp low id code read timing waveform vpp high read timing waveform tvps address valid tacc tvph tcesc tcwc toes tcep tce toes tdf toh tds tdh toe command in data out valid vcc 5v 12v vpp 0v a0 - a17 ce oe q0-q7 00h tceph1 we tacc tce tacc toe toh toh tdf manufacturer code device code c2h 3ch vid vih vil a9 a0 a1 - a8 a10-a17 ce oe q0 - q7 we vih
27 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 vpp high id code read timing waveform reset timing waveform tcwc tvps address valid 0 or 1 tacc tvph tcesc toes tcep tce toes tdf toh tds tdh toe command in data out valid vcc 5v 12v vpp 0v a0 ce oe q0-q7 90h c2h or 3ch a1 - a16 tceph2 we tvps tcwc toes tcep command in vcc 5v 12v vpp 0v ce oe q0-q7 ffh ffh a0 - a17 tcep tds tdh tds tdh command in tceph1 we
28 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 toggle bit appears in q6, when program/erase is opperating. data polling appears in q7 during pro- gramming or erase. toggle bit, data polling timing waveform high-z high-z high-z high-z data data data data out vpp 12v ce oe q6 during p/e q7 during p q7 during e q8~q15 data polling data polling program/erase complete toggle bit high we data out data out
29 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 ordering information plastic package part no. access time operating standby package erase/program current current cycle (ns) max.(ma) max.(ua) min.(time) mx28f2000tpc-90c4 90 50 100 32 pin dip 10,000 mx28f2000tpc-12c4 120 50 100 32 pin dip 10,000 mx28f2000tqc-90c4 90 50 100 32 pin plcc 10,000 MX28F2000TQC-12C4 120 50 100 32 pin plcc 10,000
30 mx28f2000t p/n: pm0472 rev. 1.0, jun 13, 1997 package information 32-pin plastic dip item millimeters inches a 42.13 max. 1.660 max. b 1.90 [ref] .075 [ref] c 2.54 [tp] .100 [tp] d .46 [typ.] .050 [typ.] e 38.07 1.500 f 1.27 [typ.] .050 [typ.] g 3.30 .25 .130 .010 h .51 [ref] .020 [ref] i 3.94 .25 1.55 .010 j 5.33 max. .210 max. k 15.22 .25 .600 .101 l 13.97 .25 .550 .010 m .25 [typ.] .010 [typ.] note: each lead certerline is located within .25mm[.01 inch] of its true position [tp] at a maximum at maximum material condition. 32-pin plastic leaded chip carrier (plcc) item millimeters inches a 12.44 .13 .490 .005 b 11.50 .13 .453 .005 c 14.04 .13 .553 .005 d 14.98 .13 .590 .005 e 1.93 .076 f 3.30 .25 .130 .010 g 2.03 .13 .080 .005 h .51 .13 .020 .005 i 1.27 [typ.] .050 [typ.] j .71 [ref] .028 [ref] k .46 [ref] .018 [ref] l 10.40/12.94 .410/.510 (w) (l) (w) (l) m .89r .035r n .25[typ.] .010[typ.] note: each lead certerline is located within .25mm[.01 inch] of its true position [tp] at a maximum at maximum material condition. 1 b a 4 5 9 13 14 17 20 21 25 29 32 cd e f g h i k j l m n 30 a 17 32 16 1 f d e c b h ij g m 0~15? k l
31 mx28f2000t m acronix i nternational c o., l td. headquarters: tel:+886-3-578-8888 fax:+886-3-578-8887 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-747-2309 fax:+65-748-4090 taipei office: tel:+886-3-509-3300 fax:+886-3-509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the rignt to change product and specifications without notice.

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